This invention relates to integrated circuit (IC) chips, and particularly to facilitation of global routing within IC chips by the inclusion of extra conductor paths or wires to library cells.
IC chips are often based on a collection of cells selected from a library. The cells are laid out and interconnected in an optimal fashion by a router to electrically connect portions of one cell to portions of another cell. Usually cell connection is accomplished on a metal wiring layer. However, if the connection pins of a cell are not easily accessible, difficulty arises in connecting the cell to the wiring layer, and hence to other cells of the chip. While connections can be planned during the initial design phase of the chip, re-working a chip design often results in changes in pin connections and locations, leading to difficulties in pin connections. To solve this problem, it is common to lay out new conductive paths over the metal layer and add conductive vias between the paths. Often new conductive paths are routed between existing paths, leading to increased congestion of the conductive paths and longer conductive runs. The existing conductive paths often require the vias be placed in inconvenient locations, adding to the length of the conductive path.
The present invention is directed to a technique of fabricating additional conductive paths or wires to library cells, presenting the ability to access cell pins at arbitrary coordinates along the path length. Additionally, vias between paths may be placed in more arbitrary locations.
According to the present invention, a metal wire for a feature of a cell is extended using a grid based on a metal layer of the cell. Each grid element is assigned one of three designators. An xe2x80x9cFxe2x80x9d designator is assigned to grid elements representing the metal wire being extended. An xe2x80x9cExe2x80x9d designator is assigned to grid elements representing blockages to extension of the metal wire, such as metal wires of other features and internal metal wires interconnecting features within the cell. A xe2x80x9cUxe2x80x9d designator is assigned to grid elements that are neither F-designated, nor E-designated grid elements. U-designated grid elements that are neighbors to E-designated grid elements are identified. A path of minimum width is defined through the U-designated grid elements that are not neighbors to E-designated grid elements between the cell boundary and a F-designated grid element.
In one form of the invention, strings of F-designated grid elements and strings of E-designated grid elements are identified in rows and columns of grid elements. Wxe2x88x921 of the F- and E-designators are changed to U-designations, where W is the minimal width of the wire, to locate grid elements that define the wire.
In another form of the invention, U-designated grid elements that are neighbors to E-designated grid elements are identified by calculating a difference between x coordinates and between the y coordinates of the U-designated grid element and the E-designated grid element. A distance is calculated which is a hypotenuse of a right triangle whose sides are based on the differences between the x and y coordinates. If at least one of the calculation results for a U-designated grid element are smaller than a predetermined value, that U-designated grid element is identified as a neighbor of the E-designated grid element.
In another form of the invention, the path is defined by identifying U-designated grid elements available for a path between the cell boundary and an F-designated grid element that are not neighbors of an E-designated grid element. A minimum path is identified through the available grid elements.
Another form of the invention concerns identification of possible vias to the metal layer through multiple layers of the cell.
In one embodiment, the invention is carried out in a computer under the control of program code that is included in a computer program embedded on a computer readable medium.